Technical Field
The present description relates to techniques for managing a plurality of hysteretic DC-DC buck converters arranged to create multiple output voltages with different point of loads or to provide a common supply current to a common load, each of said hysteretic DC-DC buck converters comprising a hysteretic comparator operating according to a respective hysteresis window.
Various embodiments may apply, e.g., to managing hysteretic converters placed on a same die or chip, DC-DC regulators, supply for power combo for hard disks.
Description of the Related Art
DC-DC buck converters are widely used to supply a lot of kinds of electronic systems, including microprocessor units (MPUs), memories and chip sets on board, because of the small size and high efficiency of such DC-DC buck converters. Due to the several applications involved, several different control loops have been designed in order to meet the specifications in terms of speed, power consumptions, output voltage accuracy. Hysteretic buck converters are well suited for microprocessor supply mainly due to their fast response to the high load current slew rate steps, maintaining the regulated output voltage. FIG. 1 shows a basic configuration of DC-DC buck converter with a hysteretic PWM controller according to the prior art. The architecture is quite simple, as the converter 10 is basically an oscillator, generating a feedback triangular waveform Vfb to be compared to a reference voltage VR through a hysteretic comparator 11, as depicted in FIG. 2.
Basically, a battery 12 generates an input voltage Vi which is coupled to an input node SW of an inductor 13 having an equivalent series resistor 15, with a resistance value RESRL, through a series switch 14a, i.e., a high side power FET, and a switch 14b, a low side power FET, connected to ground GND. The input node SW is thus a switching node, between the input voltage Vi and the ground GND. An output node O of the inductor 13 and series resistor 15 oscillating pair represents also the output node of the converter 10 at which an output voltage Vo is formed. Between the output node O and ground GND is connected an output capacitor 16 with an equivalent series resistor 17 having a resistance value RESRC. In parallel to the capacitor 16 and series resistor 17 is connected an output resistance 19, i.e., a load, with a value R. The output node O is also connected to the positive input of the hysteretic comparator 11, while its negative input is connected to the reference voltage VR, supplied by a reference generator 18. The output signal of the hysteretic voltage 11 is sent to a driver 20 which, depending on the level of the output signal of the hysteretic voltage 11, issues a PWM (pulse width modulation) driving signal Q to the series switch 14a and its negated Q to the parallel switch 14b. 
The triangular feedback waveform Vfb, which in the case of FIG. 1 corresponds to the output voltage Vo, but in general represents a feedback signal fed back through a feedback network in the feedback loop represented by the hysteretic comparator 11 and driver 20, is typically created by the equivalent series resistor 17 with value RESRC of the output capacitor 16.
For a continuous conduction mode, which means there is not a period of time in which the inductor current is continuously equal to zero, this kind of a regulator has a switching frequency FSW=1/TSW, where TSW is the period of the switching voltage VSW at the input node SW, that is based on a combination of the input voltage VI, the output voltage VO, the inductance value L of the inductor 13, and the output capacitor series resistor 17 value, RESRC. This resistor 17 generates the triangular feedback waveform Vfb, in combination with an inductor current IL going through the capacitor 16 from the inductor 13. The feedback waveform Vfb is compared with the comparator reference voltage VR by the comparator 11, in a way similar to a conventional fixed frequency voltage mode regulator. The operation of the circuit of FIG. 1 results in the following relationships for the switch-on period TON, the switch-off period TOFF and the switching period TSW of the voltage Vt in continuous current mode:
            T      ON        =                            V          HYST                                      V            I                    -                      V            O                              ⁢              L                  R          ESRC                                T      OFF        =                            V          HYST                          V          O                    ⁢              L                  R          ESRC                                T      SW        =                            T          ON                +                  T          OFF                    =                                                  V              HYST                        ⁢                          V              I                                                          (                                                V                  I                                -                                  V                  O                                            )                        ⁢                          V              O                                      ⁢                  L                      R            ESRC                              where VHYST is the amplitude of the hysteresis window, between a lower threshold VTHL and higher threshold VTHH. A good, i.e., stable, control is reached when the voltage across the series resistor 17 is much bigger than the ripple of the capacitor 16.
In modern electronics, to reduce the size of the printed circuit boards and the costs of the materials, small ceramic capacitors with very low equivalent series resistance (ESR) are commonly used; in this case the ripple of the capacitor becomes dominant on the ripple on the series resistance RESRC and the controller will tend to a LC resonant filter, with its typical phase delay and oscillating behavior.
In general the triangular feedback voltage Vfb, which is fed back to the hysteretic comparator, can differ with respect to output voltage Vo since, for instance it is known to add a simple passive ripple reconstruction network, inserting a resistor and capacitor, in parallel with the inductor winding, as disclosed in Nabeshima, T. Sato, S. Yoshida, S. Chiba and K. Onda, “Analysis and Design Considerations of a Buck Converter with a Hysteretic PWM controller” in Proceedings of Power Electronics Specialists Conference, pp. 1711-1716, 2004. In such a circuit the switching frequency is affected by the delay of the comparators and the drivers and it is also affected by the finite on resistance of the power FET (such as the switches 14a and 14b shown in FIG. 1)
When more than one hysteretic DC-DC converter is included in the same die, due to internal noise (for instance mutual inductances among bonding wires, or kick-back noise on the reference voltages when regulators are switching) or due to external noise (i.e., coupling among the PCB tracks or among inductors), such converters tend to switch together, increasing the peak and RMS supply current coming from voltage VI and, consequently, the EMI (electromagnetic interference) and the power supply bouncing (considering that interconnections are present between the input voltage VI and the high side power FETs).
In FIG. 3 is shown a time diagram illustrating the effect on the supply current of two switching converters, or regulators, such as the converter of FIG. 1, commutating at the same time. With Vfb1 is indicated the feedback voltage of a first converter, while with Vfb2 is indicated the triangular feedback voltage of a second converter. Is indicates the supply current provided from the battery (or the main input supply) to such two regulators jointly. As shown in FIG. 3, due to noise, the two converters tend to switch synchronously at a time t1 at which the switch-on period TON. This generates a spike and then a decrease of the supply current Is, while such supply current Is should more evenly distributed along the switching period. Furthermore, especially in DCM (discontinuous conduction modes) condition, the synchronized behavior could even cause a DC shift in the output voltage due to such a coupling.
The electrical simulation results of the interaction between two hysteretic DC-DC converters due to noise coupling, injected on the feedback Vfb2 of the second generator by the switching node SW of the first generator are shown in FIG. 4. In particular, in FIG. 4 are shown the time diagrams of the voltages at the switching node for each regulator respectively, VSW1 and VSW2, the inductor currents IL1 and IL2 through the respective inductors (like inductor 13 in FIG. 1), and the total supply current Is. The time window in FIG. 4 is divided in two sub-windows, a first sub-window D, for DCM (discontinuous conduction modes), and a second subwindow C, for CCM (continuous current mode).
Both in DCM and in CCM modes each switch on of the high side power FET, i.e., switch 14a in FIG. 1, of the first DC-DC converter triggers the switch on of the high side power FET of the second DC-DC converter, making them synchronized.
The resulting peak and RMS supply current Is are obviously increased with respect to not-synchronized behavior.
Document U.S. Pat. No. 6,147,478 A deals with such problem, proposing a solution directed to interleaving several hysteretic DC-DC converters in a single die. Such a solution basically provides adding a clock signal in order to trigger a switch-on period TON of the desired switching regulator at the desired frequency. The clock frequency has to be chosen higher than the maximum switching frequency that the hysteretic DC-DC converter can reach, which, as mentioned, is function of the input voltage, the output voltage, the RDSON of the FET switches of the half bridge and the ESR of the inductor.
If the clock frequency is lower than the maximum natural switching frequency of the hysteretic DC-DC converter sub-harmonic oscillations can occur, and the inductor current ripple increases as the ripple of the output voltage.